The invention pertains to a frequency divider circuit.
More specifically, the present invention relates to a frequency divider circuit for divisors consisting of an integral part and a fractional part. "ESSCIRC '82, Eighth European Solid-State Circuits Conference", Brussels, Sept. 22 through 24, 1982, pages 145 to 148, describes an arrangement of this kind which is designed as a rate multiplier. That arrangement utilizes a digital first accumulator consisting of a clocked data register and an m-bit first adder whose first input is presented with an m-bit first digital word corresponding to the fractional part of the divisor, and whose second input is fed from the output of the data register, whose input is connected to the output of the first adder.
As is well known, a rate multiplier has the property of eliminating q highly uniformly distributed pulses from p pulses of the signal to be frequency-divided, where q is smaller than p. If, for example, 66 pulses are to be eliminated during 100 input pulses, so that 33 output pulses are to be produced, the rate multiplier will provide first 32 output pulses at intervals of 3 input pulses and then 1 output pulse at an interval of 4 input pulses.
If the conventional rate multiplier is used in a phase-locked loop to produce a frequency- and phase-stable clock signal, the following problem arises: For the above duration of 32 output pulses at intervals of 3 input pulses, the phase-locked loop will adjust itself to a zero phase error if the circuit has a suitable time constant. For the duration of the four input pulses, however, a large phase error (jitter) will be present.